For example, with conventional failure analysis of a semiconductor integrated circuit (LSI chip), an available method is to use a fault simulator or the like to logically narrow down locations (logical fault candidates) that are the cause of failure in a semiconductor integrated circuit.
In a case where a semiconductor integrated circuit has a physical abnormality, failure locations can be narrowed down by an analyzer such as an emission analysis or OBIRCH analysis. For example, an image in which a hot spot has been detected can be acquired by an emission microscope, and an image in which an OBIRCH reaction has been detected can be acquired by a OBIRCH analysis.
However, although a light emission or an OBIRCH reaction (both of which shall be referred to as a “detected signal” below) is a signal from a circuit related to the location of a physical abnormality, the signal is not necessarily at the location of the physical abnormality per se. For this reason, technicians make a determination from various aspects such as layout data, logical circuit diagrams and detected signals and then estimate where abnormalities are located. Next, the physical abnormality locations are observed by observation equipment such as an FIB unit.
Such a conventional method and apparatus for failure analysis of a semiconductor integrated circuit are described in Patent Document 1. Patent Document 1 describes identifying a genuine failure location using an emission analysis and identifying the cause of the failure. Patent Document 1 describes conducting a function test of a semiconductor integrated circuit that undergoes failure analysis; specifying a node of a failure location at which a desired electrical characteristic is not obtained; acquiring an emission image by detecting a light-emission spot, which is based upon hot electrons emitted from the semiconductor integrated circuit, using an emission analysis; conducting failure analysis based upon the difference between the emission image and an emission image that results from hot electrons emitted from a conforming semiconductor integrated circuit; identifying the failure location and generating coordinate data thereof; accepting the test results of the function test and analytical results from the emission analysis and determining whether a failure has occurred in the semiconductor integrated circuit that undergoes the failure analysis; and when a failure has occurred, determining the cause of the failure.
Further, in Patent Document 1, a dust inspection for dust attached to a circuit surface is conducted at the time of the manufacturing process and the coordinates of the position of dust are detected (Paragraph No. 0019). A light-emission spot resulting from hot electrons is detected using an emission analysis, and an emission image is acquired (Paragraph No. 0025). Node data and coordinate data corresponding to the node of the circuit ahead of the node corresponding to the coordinate data of the emission spot are generated (Paragraph No. 0065). On the basis of this node data and coordinate data, the results of the dust inspection and data from a navigation tool, processing for determining whether a failure has occurred is executed and, if a failure has occurred, the coordinate data of this location is generated (Paragraph No. 0065). Further, as described in Paragraph Nos, 0021, 0022, etc., since a node possesses an electrical signal level which is an H level or an L level, it is wiring (referred to as a “net” below) connecting a transistor circuit with another transistor circuit.
[Patent Document 1]    Japanese Patent Kokai Publication No. JP2004-45132A